Title:

Asynchronous pulse logic

Author:

Nyström, Mika.

Personal Author:

Publication Information:

Boston : Kluwer Academic Publishers, [2002]

©2002

Physical Description:

xxv, 206 pages : illustrations ; 25 cm

Language:

English

Added Author:

Electronic Access:

Table of contents http://www.loc.gov/catdir/toc/fy031/2002021533.html
ISBN:

9781402070686

Format :

Book

### Available:*

Library | Call Number | Material Type | Home Location | Status | Item Holds |
---|---|---|---|---|---|

Searching... | TK7888.4 .N96 2002 | Adult Non-Fiction | Non-Fiction Area | Searching... | Searching... |

### On Order

### Summary

### Summary

This comprehensive analysis of a newly developed asynchronous circuit family covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family.

### Author Notes

Mika Nystrom is an Instructor in Computer Science at California Institute of Technology.

### Table of Contents

List of Figures | p. xi |

Preface | p. xv |

Acknowledgments | p. xxi |

First Author's Personal Thanks | p. xxiii |

1. Preliminaries | p. 1 |

1 High-speed CMOS-circuits | p. 1 |

2 Asynchronous protocols and delay-insensitive codes | p. 3 |

3 Production rules | p. 4 |

4 The MiniMIPS processor | p. 4 |

5 Commonly used abbreviations | p. 6 |

2. Asynchronous-Pulse-Logic Basics | p. 7 |

1 Road map of this chapter | p. 9 |

2 The pulse repeater | p. 10 |

2.1 Timing constraints in the pulse repeater | p. 11 |

2.2 Simulating the pulse repeater | p. 11 |

2.3 The synchronous digital model | p. 18 |

2.4 Asymmetric pulse-repeaters | p. 20 |

3 Formal model of pulse repeater | p. 21 |

3.1 Basic definitions | p. 21 |

3.2 Handling the practical simulations | p. 22 |

3.3 Expanding the model | p. 24 |

3.4 Using the extended model | p. 26 |

3.5 Noise margins | p. 28 |

4 Differential-equations treatment of pulse repeater | p. 29 |

4.1 Input behavior of pulse repeater | p. 30 |

4.2 Generalizations and restrictions | p. 34 |

3. Computing with Pulses | p. 37 |

1 A simple logic example | p. 38 |

2 Pulse-handshake duty-cycle | p. 42 |

3 Single-track-handshake interfaces | p. 45 |

4 Timing constraints and timing "assumptions" | p. 46 |

5 Minimum cycle-transition-counts | p. 47 |

6 Solutions to transition-count problem | p. 48 |

7 The APL design-style in short | p. 48 |

4. A Single-Track Asynchronous-Pulse-Logic Family: I. Basic Circuits | p. 51 |

1 Preliminaries | p. 51 |

1.1 Transition counting in pipelined asynchronous circuits | p. 52 |

1.2 Transition-count choices in pulsed circuits | p. 53 |

1.3 Execution model | p. 56 |

1.4 Capabilities of the STAPL family | p. 56 |

1.5 Design philosophy | p. 58 |

2 The basic template | p. 58 |

2.1 Bit generator | p. 59 |

2.2 Bit bucket | p. 63 |

2.3 Left-right buffer | p. 66 |

3 Summary of properties of the simple circuits | p. 71 |

5. A Single-Track Asynchronous-Pulse-Logic Family: II. Advanced Circuits | p. 73 |

1 Multiple input and output channels | p. 73 |

1.1 Naive implementation | p. 74 |

1.2 Double triggering of logic block in the naive design | p. 75 |

1.3 Solution | p. 76 |

1.4 Timing assumptions | p. 77 |

2 General logic computations | p. 77 |

2.1 Inputs whose values are not used | p. 78 |

3 Conditional communications | p. 81 |

3.1 The same program can be expressed in several ways | p. 83 |

3.2 Simple techniques for sends | p. 83 |

3.3 General techniques for conditional communications | p. 84 |

4 Storing state | p. 89 |

4.1 The general state-storing problem | p. 89 |

4.2 Implementing state variables | p. 90 |

4.3 Compiling the state bit | p. 92 |

5 Special circuits | p. 95 |

5.1 Arbitration | p. 96 |

5.2 Four-phase converters | p. 99 |

6 Resetting STAPL circuits | p. 100 |

6.1 Previously used resetting schemes | p. 101 |

6.2 An example | p. 104 |

6.3 Generating initial tokens | p. 104 |

7 How our circuits relate to the design philosophy | p. 105 |

8 Noise | p. 106 |

8.1 External noise-sources | p. 106 |

8.2 Charge sharing | p. 107 |

8.3 Crosstalk | p. 107 |

8.4 Design inaccuracies | p. 109 |

6. Automatic Generation of Asynchronous-Pulse-Logic Circuits | p. 111 |

1 Straightforwardly compiling from a higher-level specification | p. 111 |

2 An alternative compilation method | p. 113 |

3 What we compile | p. 113 |

4 The PL1 language | p. 114 |

4.1 Channels or shared variables? | p. 115 |

4.2 Simple description of the PL1 language | p. 115 |

4.3 An example: the replicator | p. 117 |

5 Compiling PL1 | p. 118 |

6 PL1-compiler front-end | p. 120 |

6.1 Determinism conditions | p. 120 |

6.2 Data encoding | p. 122 |

7 PL1-compiler back-end | p. 124 |

7.1 Slack | p. 125 |

7.2 Logic simplification | p. 127 |

7.3 Code generation | p. 129 |

7. A Design Example: The Spam Microprocessor | p. 133 |

1 The SPAM architecture | p. 133 |

2 SPAM implementation | p. 134 |

2.1 Decomposition | p. 134 |

2.2 Arbitrated branch-delay | p. 136 |

2.3 Byte skewing | p. 137 |

3 Design examples | p. 140 |

3.1 The PCUNIT | p. 140 |

3.2 The REGFILE | p. 151 |

4 Performance measurements on the SPAM implementation | p. 158 |

4.1 Straightline program | p. 158 |

4.2 Computing Fibonacci numbers | p. 160 |

4.3 Energy measurements | p. 162 |

4.4 Summary of SPAM implementation's performance | p. 163 |

4.5 Comparison with QDI | p. 163 |

8. Related Work | p. 167 |

1 Theory | p. 167 |

2 STAPL circuit family | p. 167 |

3 PL1 language | p. 169 |

4 SPAM microprocessor | p. 170 |

9. Lessons Learned | p. 171 |

1 Conclusion | p. 172 |

Appendices | p. 173 |

PL1 Report | p. 173 |

0.1 Scope | p. 173 |

0.2 Structure of PL1 | p. 173 |

1 Syntax elements | p. 174 |

1.1 Keywords | p. 174 |

1.2 Comments | p. 174 |

1.3 Numericals | p. 174 |

1.4 Identifiers | p. 174 |

1.5 Reserved special operators | p. 174 |

1.6 Expression operators | p. 174 |

1.7 Expression syntax | p. 175 |

1.8 Actions | p. 175 |

2 PL1 process description | p. 176 |

2.1 Declarations | p. 176 |

2.2 Communication statement | p. 176 |

2.3 Process communication-block | p. 176 |

3 Semantics | p. 178 |

3.1 Expression semantics | p. 178 |

3.2 Action semantics | p. 180 |

3.3 Execution semantics | p. 180 |

3.4 Invariants | p. 181 |

3.5 Semantics in terms of CHP | p. 181 |

3.6 Slack elasticity | p. 183 |

4 Examples | p. 184 |

SPAM Processor Architecture Definition | p. 187 |

1 SPAM overview | p. 187 |

2 SPAM instruction format | p. 187 |

3 SPAM instruction semantics | p. 189 |

3.1 Operand generation | p. 189 |

3.2 Operation definitions | p. 189 |

4 Assembly-language conventions | p. 191 |

4.1 The SPAM assembly format | p. 191 |

Proof that Definition 2.2 Defines a Partial Order | p. 193 |

1 Remark on Continuity | p. 194 |