Cover image for Asynchronous pulse logic
Title:
Asynchronous pulse logic
Author:
Nyström, Mika.
Personal Author:
Publication Information:
Boston : Kluwer Academic Publishers, [2002]

©2002
Physical Description:
xxv, 206 pages : illustrations ; 25 cm
Language:
English
Added Author:
Electronic Access:
Table of contents http://www.loc.gov/catdir/toc/fy031/2002021533.html
ISBN:
9781402070686
Format :
Book

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Summary

Summary

This comprehensive analysis of a newly developed asynchronous circuit family covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family.


Author Notes

Mika Nystrom is an Instructor in Computer Science at California Institute of Technology.


Table of Contents

List of Figuresp. xi
Prefacep. xv
Acknowledgmentsp. xxi
First Author's Personal Thanksp. xxiii
1. Preliminariesp. 1
1 High-speed CMOS-circuitsp. 1
2 Asynchronous protocols and delay-insensitive codesp. 3
3 Production rulesp. 4
4 The MiniMIPS processorp. 4
5 Commonly used abbreviationsp. 6
2. Asynchronous-Pulse-Logic Basicsp. 7
1 Road map of this chapterp. 9
2 The pulse repeaterp. 10
2.1 Timing constraints in the pulse repeaterp. 11
2.2 Simulating the pulse repeaterp. 11
2.3 The synchronous digital modelp. 18
2.4 Asymmetric pulse-repeatersp. 20
3 Formal model of pulse repeaterp. 21
3.1 Basic definitionsp. 21
3.2 Handling the practical simulationsp. 22
3.3 Expanding the modelp. 24
3.4 Using the extended modelp. 26
3.5 Noise marginsp. 28
4 Differential-equations treatment of pulse repeaterp. 29
4.1 Input behavior of pulse repeaterp. 30
4.2 Generalizations and restrictionsp. 34
3. Computing with Pulsesp. 37
1 A simple logic examplep. 38
2 Pulse-handshake duty-cyclep. 42
3 Single-track-handshake interfacesp. 45
4 Timing constraints and timing "assumptions"p. 46
5 Minimum cycle-transition-countsp. 47
6 Solutions to transition-count problemp. 48
7 The APL design-style in shortp. 48
4. A Single-Track Asynchronous-Pulse-Logic Family: I. Basic Circuitsp. 51
1 Preliminariesp. 51
1.1 Transition counting in pipelined asynchronous circuitsp. 52
1.2 Transition-count choices in pulsed circuitsp. 53
1.3 Execution modelp. 56
1.4 Capabilities of the STAPL familyp. 56
1.5 Design philosophyp. 58
2 The basic templatep. 58
2.1 Bit generatorp. 59
2.2 Bit bucketp. 63
2.3 Left-right bufferp. 66
3 Summary of properties of the simple circuitsp. 71
5. A Single-Track Asynchronous-Pulse-Logic Family: II. Advanced Circuitsp. 73
1 Multiple input and output channelsp. 73
1.1 Naive implementationp. 74
1.2 Double triggering of logic block in the naive designp. 75
1.3 Solutionp. 76
1.4 Timing assumptionsp. 77
2 General logic computationsp. 77
2.1 Inputs whose values are not usedp. 78
3 Conditional communicationsp. 81
3.1 The same program can be expressed in several waysp. 83
3.2 Simple techniques for sendsp. 83
3.3 General techniques for conditional communicationsp. 84
4 Storing statep. 89
4.1 The general state-storing problemp. 89
4.2 Implementing state variablesp. 90
4.3 Compiling the state bitp. 92
5 Special circuitsp. 95
5.1 Arbitrationp. 96
5.2 Four-phase convertersp. 99
6 Resetting STAPL circuitsp. 100
6.1 Previously used resetting schemesp. 101
6.2 An examplep. 104
6.3 Generating initial tokensp. 104
7 How our circuits relate to the design philosophyp. 105
8 Noisep. 106
8.1 External noise-sourcesp. 106
8.2 Charge sharingp. 107
8.3 Crosstalkp. 107
8.4 Design inaccuraciesp. 109
6. Automatic Generation of Asynchronous-Pulse-Logic Circuitsp. 111
1 Straightforwardly compiling from a higher-level specificationp. 111
2 An alternative compilation methodp. 113
3 What we compilep. 113
4 The PL1 languagep. 114
4.1 Channels or shared variables?p. 115
4.2 Simple description of the PL1 languagep. 115
4.3 An example: the replicatorp. 117
5 Compiling PL1p. 118
6 PL1-compiler front-endp. 120
6.1 Determinism conditionsp. 120
6.2 Data encodingp. 122
7 PL1-compiler back-endp. 124
7.1 Slackp. 125
7.2 Logic simplificationp. 127
7.3 Code generationp. 129
7. A Design Example: The Spam Microprocessorp. 133
1 The SPAM architecturep. 133
2 SPAM implementationp. 134
2.1 Decompositionp. 134
2.2 Arbitrated branch-delayp. 136
2.3 Byte skewingp. 137
3 Design examplesp. 140
3.1 The PCUNITp. 140
3.2 The REGFILEp. 151
4 Performance measurements on the SPAM implementationp. 158
4.1 Straightline programp. 158
4.2 Computing Fibonacci numbersp. 160
4.3 Energy measurementsp. 162
4.4 Summary of SPAM implementation's performancep. 163
4.5 Comparison with QDIp. 163
8. Related Workp. 167
1 Theoryp. 167
2 STAPL circuit familyp. 167
3 PL1 languagep. 169
4 SPAM microprocessorp. 170
9. Lessons Learnedp. 171
1 Conclusionp. 172
Appendicesp. 173
PL1 Reportp. 173
0.1 Scopep. 173
0.2 Structure of PL1p. 173
1 Syntax elementsp. 174
1.1 Keywordsp. 174
1.2 Commentsp. 174
1.3 Numericalsp. 174
1.4 Identifiersp. 174
1.5 Reserved special operatorsp. 174
1.6 Expression operatorsp. 174
1.7 Expression syntaxp. 175
1.8 Actionsp. 175
2 PL1 process descriptionp. 176
2.1 Declarationsp. 176
2.2 Communication statementp. 176
2.3 Process communication-blockp. 176
3 Semanticsp. 178
3.1 Expression semanticsp. 178
3.2 Action semanticsp. 180
3.3 Execution semanticsp. 180
3.4 Invariantsp. 181
3.5 Semantics in terms of CHPp. 181
3.6 Slack elasticityp. 183
4 Examplesp. 184
SPAM Processor Architecture Definitionp. 187
1 SPAM overviewp. 187
2 SPAM instruction formatp. 187
3 SPAM instruction semanticsp. 189
3.1 Operand generationp. 189
3.2 Operation definitionsp. 189
4 Assembly-language conventionsp. 191
4.1 The SPAM assembly formatp. 191
Proof that Definition 2.2 Defines a Partial Orderp. 193
1 Remark on Continuityp. 194