Cover image for Exploring programmable ICs
Title:
Exploring programmable ICs
Author:
Pepper, Clement S.
Personal Author:
Publication Information:
Indianapolis, IN : Prompt Publications, [2001]

©2001
Physical Description:
xviii, 344 pages : illustrations ; 24 cm
Language:
English
ISBN:
9780790612089
Format :
Book

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TK7872.L64 P47 2001 Adult Non-Fiction Non-Fiction Area
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Summary

Summary

Programmable ICs are devices designed for operation under program control from a computer or microcontroller. This book takes the reader through an introduction to the world of ICs, and explores varied programmable ICs along with selected applications with relevance to popular projects.


Author Notes

Clement S. Pepper has more than 30 years of experience in electronics RandD, working as an electrical drafter, a design engineer, and in other capacities before becoming the manager of engineering and manufacturing for Intelcom Rad Tech. He holds a bachelor's degree in physics with a concentration in electronics from San Diego State University


Table of Contents

Prefacep. xiii
About the Authorp. xvii
1 What We Need To Get Startedp. 1
Introductionp. 2
Some Construction and Use Tipsp. 16
2 The Analog Devices AD588 "DACPORT"p. 17
Introductionp. 18
Referencesp. 23
3 The TR1602/AY-5-1013 UARTp. 25
Introductionp. 26
Asynchronous Data Transfer With the TR1602/AY-5-1013p. 33
TR1602/AY-5-1013 Operationp. 35
Bench-Top Setup and Operationp. 44
4 The SY6522/SY6522A VIAp. 49
Introductionp. 50
Theory of Operationp. 51
The 6522 Registersp. 58
Port A and B Registersp. 61
Handshake Control of Data Transfersp. 66
Read Handshakep. 66
Write Handshakep. 66
Latch and Counter Registersp. 67
Timer/Counter 1 Functionsp. 68
Timer 1 One-Shot Modep. 69
Timer 1 Free-Run Modep. 71
Timer/Counter 2 Functionsp. 72
Timer 2 One-Shot Modep. 72
Timer 2 Pulse-Counting Modep. 74
Shift Register Operationp. 74
Mode 001p. 74
Mode 010p. 76
Mode 011p. 76
Mode 100p. 78
Mode 101p. 78
Mode 110p. 78
Mode 111p. 78
Interrupt Operationp. 79
Bench-Top Operation of the 6522p. 84
5 The R6520/ MC6820/MC6821 PIAp. 97
Introductionp. 98
Theory of Operationp. 100
PIA to MPU Interface Signalsp. 102
The Bidirectional Data Bus (00-07)p. 104
Enable (E)p. 104
Read/Write (R//W)p. 104
RESET (Active Low)p. 104
Chip Selects (CS0, CS1, /CS2)p. 105
Register Selects (RS0, RS1)p. 108
Interrupt Request (/IRQA, /IRQB)p. 108
PIA Peripheral Interface Linesp. 108
Port A Peripheral Data (PA0-PA7)p. 109
Port B Peripheral Data (PB0-PB7)p. 109
Interrupt Input (CA1 and CB1)p. 109
Peripheral Control (CA2)p. 110
Peripheral Control (CB2)p. 110
Internal Controlsp. 110
Initializationp. 110
Port A-B Hardware Characteristicsp. 110
Control Registers CRA and CRBp. 111
Data Direction Access Control Bit, CRA-2 and CRB-2p. 111
Interrupt Flags, CRA-6, CRA-7, CRB-6, CRB-7p. 112
Control of CA2 and CB2 Peripheral Control Lines CRA-3, CRA-4, CRA-5, CRB-3, CRB-4, CRB-5p. 112
Control of CA1 and CB1 Interrupt Lines CRA-0, CRB-0, CRA-1, CRB-1p. 112
Bench-Top Operation of the 6520/6820/6821p. 112
6 The INS8250, INS8250-B, NS16450, INS8250A, NS16C450, and INS82C50A UARTsp. 123
Introductionp. 124
UART Pin Descriptionsp. 139
UART Registersp. 143
Line Control Registerp. 144
Programmable Baud Generatorp. 145
Line Status Registerp. 146
Interrupt Identification Registerp. 147
Interrupt Enable Registerp. 148
Modem Control Registerp. 149
Modem Status Registerp. 150
Manufacturing Summaryp. 151
INS8250 and INS8250-B Functional Considerationsp. 152
INS8250A and NS16450 Functional Considerationsp. 153
INS8250A and NS16450 Timing Considerationsp. 153
Software Compatibilityp. 154
Using the INS8250A, NS16450, INS82C50A, and NS16C450 With Edge-Triggered ICUsp. 154
Creating an Interrupt Edge Via Softwarep. 158
Creating an Interrupt Edge in Hardwarep. 160
Bench-Top Operation of the INS8250-B/NS16450 UARTp. 160
7 The NS16550/NS16550A/NS16550AF UART With FIFOsp. 169
Introductionp. 170
UART Pin Descriptionsp. 189
UART Registersp. 193
Line Control Registerp. 193
Programmable Baud Generatorp. 195
Line Status Registerp. 195
The FIFO Control Register (Write Only)p. 197
Interrupt Identification Registerp. 198
Interrupt Enable Registerp. 199
Modem Control Registerp. 199
Modem Status Registerp. 200
Scratchpad Registerp. 201
FIFO Interrupt Mode Operationp. 202
FIFO Polled Mode Operationp. 203
NS16550/A/AF and NS16550 Functional and Timing Considerationsp. 204
Bench-Top Operation of the NS16550A/AF UARTp. 204
8 The 8251/8251A USARTp. 221
Introductionp. 222
USART Pin Descriptionsp. 239
Read/Write Control Logicp. 239
Modem Controlp. 240
Transmit Bufferp. 240
Receive Bufferp. 241
Operating the 8251/8251A USARTp. 243
Operational Start-Up Requirementsp. 243
USART Programmingp. 243
Mode Instructionp. 244
Command Instructionp. 244
Mode Instruction Definitionp. 244
Asynchronous Transmissionp. 245
Asynchronous Receivep. 245
Synchronous Transmissionp. 246
Synchronous Receivep. 246
Command Instruction Formatp. 247
Status Read Formatp. 248
Parity Errorp. 248
Overrun Errorp. 248
Framing Errorp. 248
Bench-Top Operation of the 8251/8251A USARTp. 249
9 The 8253/8253-5 Programmable Interval Timerp. 261
Introductionp. 262
The 8253 System Interfacep. 262
Functional Descriptionp. 263
Data Bus Bufferp. 265
Read/Write Logicp. 265
Read (/RD)p. 265
Write (/WR)p. 266
Addressing (A0, A1)p. 266
Chip Select (/CS)p. 266
The Control Word Registerp. 266
Counter #0, Counter #1, and Counter #2p. 266
8253 Operational Descriptionp. 267
Programming the 8253p. 268
SC - Select Counterp. 269
RL - Read/Loadp. 269
Mode Definitionp. 269
Mode 0 Interrupt on Terminal Countp. 269
Mode 1 Programmable One-Shotp. 272
Mode 2 Rate Generatorp. 272
Mode 3 Square-Wave Generatorp. 272
Mode 4 Software-Triggered Strobep. 273
Mode 5 Hardware-Triggered Strobep. 273
The 8253 Read/Write Procedurep. 273
Write Operationsp. 273
Read Operationsp. 275
Reading While Countingp. 276
Mode Register for Latching Countp. 279
8253 Timing and AC Characteristicsp. 279
Bench-Top Operation of the 8253/8253-5 Programmable Interval Timerp. 279
10 The 8254/8254-2 Programmable Interval Timerp. 291
Introductionp. 292
The 8254 System Interfacep. 292
Functional Descriptionp. 293
Data Bus Bufferp. 293
Read/Write Logicp. 295
Read (/RD)p. 295
Write (/WR)p. 295
Addressing (A0,A1)p. 296
Chip Select (/CS)p. 296
The Control Word Registerp. 296
Counter #0, Counter #1, and Counter #2p. 296
8254 Operational Descriptionp. 298
Programming the 8254p. 299
SC - Select Counterp. 299
RW - Read/Writep. 300
Write Operationsp. 300
Read Operationsp. 302
Counter Latch Commandp. 302
Read-Back Commandp. 304
Mode Definitionsp. 307
Mode 0 Interrupt on Terminal Countp. 308
Mode 1 Programmable One-Shotp. 310
Mode 2 Rate Generatorp. 310
Mode 3 Square-Wave Generatorp. 312
Mode 4 Software-Triggered Strobep. 317
Mode 5 Hardware-Triggered Strobe (Retriggerable)p. 320
Gatep. 322
Counterp. 322
8254 Timing and AC Characteristicsp. 325
Bench-Top Operation of the 8254/8254-2 Programmable Interval Timerp. 325
Indexp. 335