Cover image for System-on-a-chip : design and test
Title:
System-on-a-chip : design and test
Author:
Rajsuman, Rochit.
Personal Author:
Publication Information:
Boston, MA : Artech House, 2000.
Physical Description:
xiii, 277 pages : illustrations ; 24 cm.
Language:
English
ISBN:
9781580531078
Format :
Book

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Summary

Summary

Starting with a basic overview of system-on-a-chip (SoC) including definitions of related terms, this text explains SoC design challenges, together with developments in SoC design and and test methodologies.


Author Notes

Rochit Rajsuman received his B.Tech. in Electrical Engineering from K.N. Institute of Technology, India, his M.S. in Electrical Engineering from the University of Oklahoma, and his Ph.D. in Electrical Engineering from Colorado State University.

Rajsuman manages test research at Advantest America R & D Center in Santa Clara, California. He is a senior member of the IEEE and a Golden Core member of the Computer Society.

050


Table of Contents

Prefacep. xi
Acknowledgmentp. xiii
Part I Designp. 1
1 Introductionp. 3
1.1 Architecture of the Present-Day SoCp. 5
1.2 Design Issues of SoCp. 8
1.3 Hardware-Software Codesignp. 14
1.3.1 Codesign Flowp. 15
1.3.2 Codesign Toolsp. 18
1.4 Core Libraries, EDA Tools, and Web Pointersp. 21
1.4.1 Core Librariesp. 21
1.4.2 EDA Tools and Vendorsp. 23
1.4.3 Web Pointersp. 28
Referencesp. 29
2 Design Methodology for Logic Coresp. 33
2.1 SoC Design Flowp. 34
2.2 General Guidelines for Design Reusep. 36
2.2.1 Synchronous Designp. 36
2.2.2 Memory and Mixed-Signal Designp. 36
2.2.3 On-Chip Busesp. 38
2.2.4 Clock Distributionp. 39
2.2.5 Clear/Set/Reset Signalsp. 40
2.2.6 Physical Designp. 40
2.2.7 Deliverable Modelsp. 42
2.3 Design Process for Soft and Firm Coresp. 43
2.3.1 Design Flowp. 43
2.3.2 Development Process for Soft/Firm Coresp. 45
2.3.3 RTL Guidelinesp. 46
2.3.4 Soft/Firm Cores Productizationp. 47
2.4 Design Process for Hard Coresp. 47
2.4.1 Unique Design Issues in Hard Coresp. 47
2.4.2 Development Process for Hard Coresp. 49
2.5 Sign-Off Checklist and Deliverablesp. 51
2.5.1 Sign-Off Checklistp. 51
2.5.2 Soft Core Deliverablesp. 52
2.5.3 Hard Core Deliverablesp. 53
2.6 System Integrationp. 53
2.6.1 Designing With Hard Coresp. 53
2.6.2 Designing With Soft Coresp. 54
2.6.3 System Verificationp. 54
Referencesp. 55
3 Design Methodology for Memory and Analog Coresp. 57
3.1 Why Large Embedded Memoriesp. 57
3.2 Design Methodology for Embedded Memoriesp. 59
3.2.1 Circuit Techniquesp. 61
3.2.2 Memory Compilerp. 66
3.2.3 Simulation Modelsp. 70
3.3 Specifications of Analog Circuitsp. 72
3.3.1 Analog-to-Digital Converterp. 72
3.3.2 Digital-to-Analog Converterp. 75
3.3.3 Phase-Locked Loopsp. 78
3.4 High-Speed Circuitsp. 79
3.4.1 Rambus ASIC Cellp. 79
3.4.2 IEEE 1394 Serial Bus (Firewire) PHY Layerp. 80
3.4.3 High-Speed I/Op. 81
Referencesp. 81
4 Design Validationp. 85
4.1 Core-Level Validationp. 86
4.1.1 Core Validation Planp. 86
4.1.2 Testbenchesp. 88
4.1.3 Core-Level Timing Verificationp. 90
4.2 Core Interface Verificationp. 93
4.2.1 Protocol Verificationp. 94
4.2.2 Gate-Level Simulationp. 95
4.3 SoC Design Validationp. 95
4.3.1 Cosimulationp. 97
4.3.2 Emulationp. 101
4.3.3 Hardware Prototypesp. 101
Referencep. 103
5 Core and SoC Design Examplesp. 105
5.1 Microprocessor Coresp. 105
5.1.1 V830R/AV Superscaler RISC Corep. 109
5.1.2 Design of PowerPC 603e G2 Corep. 110
5.2 Comments on Memory Core Generatorsp. 112
5.3 Core Integration and On-Chip Busp. 113
5.4 Examples of SoCp. 115
5.4.1 Media Processorsp. 116
5.4.2 Testability of Set-Top Box SoCp. 121
Referencesp. 122
Part II Testp. 123
6 Testing of Digital Logic Coresp. 125
6.1 SoC Test Issuesp. 126
6.2 Access, Control, and Isolationp. 128
6.3 IEEE P1500 Effortp. 129
6.3.1 Cores Without Boundary Scanp. 132
6.3.2 Core Test Languagep. 135
6.3.3 Cores With Boundary Scanp. 135
6.4 Core Test and IP Protectionp. 138
6.5 Test Methodology for Design Reusep. 142
6.5.1 Guidelines for Core Testabilityp. 142
6.5.2 High-Level Test Synthesisp. 143
6.6 Testing of Microprocessor Coresp. 144
6.6.1 Built-in Self-Test Methodp. 144
6.6.2 Example: Testability Features of ARM Processor Corep. 147
6.6.3 Debug Support for Microprocessor Coresp. 150
Referencesp. 152
7 Testing of Embedded Memoriesp. 155
7.1 Memory Fault Models and Test Algorithmsp. 156
7.1.1 Fault Modelsp. 156
7.1.2 Test Algorithmsp. 157
7.1.3 Effectiveness of Test Algorithmsp. 160
7.1.4 Modification With Multiple Data Backgroundp. 161
7.1.5 Modification for Multiport Memoriesp. 161
7.1.6 Algorithm for Double-Buffered Memoriesp. 161
7.2 Test Methods for Embedded Memoriesp. 162
7.2.1 Testing Through ASIC Functional Testp. 163
7.2.2 Test Application by Direct Accessp. 164
7.2.3 Test Application by Scan or Collar Registerp. 164
7.2.4 Memory Built-in Self-Testp. 164
7.2.5 Testing by On-Chip Microprocessorp. 169
7.2.6 Summary of Test Methods for Embedded Memoriesp. 171
7.3 Memory Redundancy and Repairp. 171
7.3.1 Hard Repairp. 171
7.3.2 Soft Repairp. 175
7.4 Error Detection and Correction Codesp. 175
7.5 Production Testing of SoC With Large Embedded Memoryp. 176
Referencesp. 177
8 Testing of Analog and Mixed-Signal Coresp. 181
8.1 Analog Parameters and Characterizationp. 182
8.1.1 Digital-to-Analog Converterp. 182
8.1.2 Analog-to-Digital Converterp. 184
8.1.3 Phase-Locked Loopp. 188
8.2 Design-for-Test and Built-in Self-Test Methods for Analog Coresp. 191
8.2.1 Fluence Technology's Analog BISTp. 192
8.2.2 LogicVision's Analog BISTp. 192
8.2.3 Testing by On-Chip Microprocessorp. 195
8.2.4 IEEE P1149.4p. 197
8.3 Testing of Specific Analog Circuitsp. 200
8.3.1 Rambus ASIC Cellp. 200
8.3.2 Testing of 1394 Serial Bus/Firewirep. 201
Referencesp. 204
9 Iddq Testingp. 207
9.1 Physical Defectsp. 207
9.1.1 Bridging (Shorts)p. 208
9.1.2 Gate-Oxide Defectsp. 212
9.1.3 Open (Breaks)p. 213
9.1.4 Effectiveness of Iddq Testingp. 215
9.2 Iddq Testing Difficulties in SoCp. 218
9.3 Design-for-Iddq-Testingp. 224
9.4 Design Rules for Iddq Testingp. 228
9.5 Iddq Test Vector Generationp. 230
Referencesp. 234
10 Production Testingp. 239
10.1 Production Test Flowp. 239
10.2 At-Speed Testingp. 241
10.2.1 RTD and Dead Cyclesp. 241
10.2.2 Fly-Byp. 243
10.2.3 Speed Binningp. 245
10.3 Production Throughput and Material Handlingp. 246
10.3.1 Test Logisticsp. 246
10.3.2 Tester Setupp. 247
10.3.3 Multi-DUT Testingp. 248
Referencesp. 249
11 Summary and Conclusionsp. 251
11.1 Summaryp. 251
11.2 Future Scenariosp. 254
Appendix RTL Guidelines for Design Reusep. 257
A.1 Naming Conventionp. 257
A.2 General Coding Guidelinesp. 258
A.3 RTL Development for Synthesisp. 260
A.4 RTL Checksp. 262
About the Authorp. 265
Indexp. 267