Cover image for Self-checking and fault-tolerant digital design
Title:
Self-checking and fault-tolerant digital design
Author:
Lala, Parag K., 1948-
Personal Author:
Publication Information:
San Francisco : Morgan Kaufmann, [2001]

©2001
Physical Description:
xii, 216 pages : illustrations ; 25 cm
Language:
English
ISBN:
9780124343702
Format :
Book

Available:*

Library
Call Number
Material Type
Home Location
Status
Central Library TK7888.3 .L274 2001 Adult Non-Fiction Non-Fiction Area
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Summary

Summary


With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips, fault-tolerant, self-checking mechanisms must be built in to assure reliable operation.


Self-Checking and Fault-Tolerant Digital Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems.


Author Notes

The author is currently a Professor in the Department of Electrical Engineering at North Carolina A&T State University. He is the author of more than 75 papers, and three books published by Prentice Hall. His research interests include design for testability, self-checking logic design, automatic logic synthesis of low power logic circuits, andCPLD/FPGA based system design. He received a M.S. from King's College, London, and a Ph.D. from the City University of London.


Table of Contents

Chapter 1 Fundamentals of Reliability
Chapter 2 Error Detecting and Correcting Codes
Chapter 3 Self-Checking Combinational Logic Design
Chapter 4 Self-Checking Checkers
Chapter 5 Self-Checking Sequential Circuit Design
Chapter 6 Fault-Tolerant Design Appendix Markov Models

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