Cover image for AGP system architecture
AGP system architecture
Dzatko, Dave.
Personal Author:
Second edition.
Publication Information:
Reading, Mass. : Addison-Wesley, [2000]

Physical Description:
xxv, 373 pages : illustrations ; 24 cm.
General Note:
Includes index.
Added Author:
Added Corporate Author:
Format :


Call Number
Material Type
Home Location
Item Holds
T385 .D988 2000 Adult Non-Fiction Central Closed Stacks

On Order



The Accelerated Graphics Port (AGP) interface is a platform bus specification that enables high-performance graphics capabilities, 3-D, and video-over networks as well as on individual PCs. This book provides an overview of the technology, a detailed description of the specification, a discussion of AGP Pro, and a tutorial for mastering AGP.

Author Notes

Dave Dzatko has over ten years of experience designing and testing computer systems. He is currently an instructor with MindShare, Inc., teaching computer architecture to leading companies in the computer industry.
Tom Shanley is one of the world's foremost authorities on PC system architecture and has personally trained thousands of engineers in hardware and software design.

Table of Contents

About This Book
The MindShare Architecture Seriesp. 1
Cautionary Notep. 2
Organization of This Bookp. 2
Who This Book Is Forp. 4
Prerequisite Knowledgep. 4
Documentation Conventionsp. 4
Visit Our Web Sitep. 7
We Want Your Feedbackp. 7
Chapter 1 The 3D Graphics Challenge
3D Graphics: Compute- and Memory-Intensivep. 9
Chapter 2 PCI/AGP Adapter Overview
System Overviewp. 15
Local Versus Main Memoryp. 20
PCI Graphics Adapterp. 23
Intro To AGP Graphics Adapterp. 25
Chapter 3 AGP Enumeration and Configuration
Example Enumeration/Configuration of AGPp. 29
Host/PCI Bridge: PCI Bus 0, Device 0, Function 0p. 29
AGP Enable/Disable Bitp. 32
Discovering Host/PCI Bridge's AGP Register Setp. 33
NB Connects To AGP Bus via PCI-to-PCI Bridgep. 35
PCI-to-PCI Bridge's Configuration Registersp. 36
Assigning AGP Bus Numberp. 40
Device At Other End of Bus Needn't Be a Graphics Adapterp. 40
Discovering AGP Graphics Adapterp. 42
Discovering Adapter's AGP Capability Register Setp. 42
Setting Up Adapter's BAR Registersp. 44
The Adapter's Command and Status Registersp. 45
Chapter 4 AGP Memory Allocation and Usage
Introduction To Dynamic Memory Allocationp. 49
AGP Aperture Implementationp. 52
Chapter 5 Window's Use of AGP
Intro To Windows Software Environmentp. 61
BIOS Initialization Requirementsp. 68
Operating System Initialization Requirementsp. 69
Chapter 6 PCI Protocol Review
Some Basic Rules For Both Reads and Writesp. 72
Example Single Data Phase Readp. 72
Example Burst Readp. 74
Treatment of Byte Enables During Read or Writep. 78
Performance During Read Transactionsp. 81
Example Single Data Phase Write Transactionp. 82
Example Burst Write Transactionp. 84
Performance During Write Transactionsp. 88
PCI Is Not An Efficient Busp. 90
Chapter 7 Intro to AGP Concepts and Terminology
Decoupling Address and Data Phases Optimizes Bus Usagep. 94
Bus Arbitrationp. 96
Issuing Transaction Requestsp. 99
AGP Data Transactionsp. 104
PCI Bus Master Can Write to AGP Adapter's Local Memoryp. 121
GART Support for PCI Masters Is Optionalp. 121
Monochrome Device Adapter (MDA) Supportp. 122
Some Terminologyp. 122
Chapter 8 The Signal Groups
Required Versus Optional Featuresp. 125
PCI Target Latency Rules Don't Apply to North Bridgep. 127
AGP Graphics Adapter Cannot Use Subtractive Decodep. 127
North Bridge/AGP Adapter Interconnect Examplesp. 127
Introduction To Signal Descriptionp. 139
AGP Clock Signalp. 139
Reset (RST#)p. 139
The Signaling Environment (I/O Voltage)p. 140
Where Is the AGP Bus Arbiter Located?p. 140
Signal Usage In AGP Transactionsp. 141
Signal Usage In PCI Transactionsp. 160
Signal Usage in Fast Write Transactionsp. 162
Special Overflow Prevention Signalsp. 166
Unimplemented PCI Signalsp. 169
Interrupt Generationp. 169
Error Reportingp. 170
USB-Related Signalsp. 172
Power Managementp. 172
Signal Typesp. 173
Pull-Up and Pull-Down Resistor Valuesp. 175
Chapter 9 The Signaling Environment
Point-to-Point Topologyp. 177
Number of Devicesp. 178
Signal Routing and Layoutp. 178
Trace Impedance and Line Terminationp. 179
Add-in Card Clock Skew Specificationsp. 179
AGP Voltage Characteristicsp. 179
Vref Generationp. 180
Component Pinout Recommendationsp. 182
Motherboard/Add-in Card Interoperabilityp. 182
Pull-up/Pull-down Resistorsp. 183
Maximum AC Ratings and Device Protectionp. 184
Power Supplyp. 184
Mechanicalsp. 184
Connector Pinoutp. 185
DC Specificationsp. 188
1x Transfer Mode Timing Parametersp. 189
2x and 4x Transfer Mode Timing Modelp. 191
Driver Characteristicsp. 205
Receiver Characteristicsp. 206
Changes to Clock Frequencies in Mobile Designsp. 206
Chapter 10 Intro To AGP Transfer Types
Command Types and the Transfer Lengthp. 207
AGP Ordering Rulesp. 212
Fence Commandp. 216
Flush Commandp. 217
Chapter 11 AGP Arbitration
The AGP Arbiterp. 219
Maximizing Bus Usage via GNT# Pipeliningp. 223
Chapter 12 AGP Request Transactions
Two Request Generation Mechanismsp. 227
AGP Request Queue Depthp. 230
Issuing Transaction Requests via AD and C/BE busesp. 231
Issuing Transaction Requests via the SBA Portp. 243
Chapter 13 AGP Data Flow Control
Introductionp. 257
In AGP, Data Is Transferred in Blocksp. 257
Wait State Before First Data Blockp. 258
Inserting Wait States Between Blocksp. 258
Data Transfer Size Can Be Less Than a Data Blockp. 260
Usage of Byte Enablesp. 261
But Minimum Data Transaction Is One Clock Longp. 261
Three Times Where Data Transfer Can Be Delayedp. 261
AGP Adapter's Control of Data Transfersp. 262
North Bridge's Control of Data Transfersp. 265
RBF# Prevents Return of Low-Priority Read Datap. 266
Chapter 14 1x Data Transactions
Introductionp. 269
Generalp. 269
Multiple Data Block Read Transactionp. 270
Multiple Block Read Data Transfer with Wait Statesp. 272
Read Data Transaction, Wait State Before First Blockp. 276
Write Data Transaction, No Initial Wait Statep. 279
Back-to-Back Write Data Transactions, No Delaysp. 281
Chapter 15 2x Data Transactions
Introductionp. 287
2x Transfer Mode Data Transactionsp. 287
Back-to-Back Read Transfers, No Wait Statesp. 289
Multiple Block Read, No Wait Statesp. 292
Multiple Block Write with Wait Statesp. 295
Back-to-Back Write Data Transactions, Minimum Delayp. 298
Chapter 16 4x Data Transactions
Introductionp. 303
Generalp. 303
Using Strobe Falling-Edges To Latch Datap. 304
Using Strobe Crossover Point to Latch Datap. 304
Back-to-Back Read Data Transactions, No Wait Statesp. 306
Multiple Block Read, No Wait Statesp. 309
Multi-Block Read with Wait State Before 2nd Data Blockp. 312
Back-to-Back Write Data Transactions, No Wait Statesp. 314
Chapter 17 Fast Write Transactions
Use of WBF# to Prevent Start of Fast Writep. 319
Arbitration to Perform a Fast Writep. 319
Introduction to the Fast Write Transactionp. 320
Fast Write Transactions in 2x Modep. 321
Fast Write Transactions in 4x Modep. 328
Adapter-Initiated Premature Transaction Terminationp. 330
Master-Initiated Premature Transaction Terminationp. 340
Back-to-Back Fast Write Transactionsp. 342
Two Fast Write Transactions with No Idle in Betweenp. 346
Use of the WBF# Signalp. 349
Short, Fast Write Transactions and DEVSEL#p. 352
Chapter 18 Collision Avoidance
Many Transaction Pairs Require Turnaround Cycle(s)p. 355
AGP Write Data Followed by Fast Writep. 356
AGP Write Data Followed by AGP Read Datap. 358
Chapter 19 AGP Pro
The Problemp. 359
AGP Pro Connectorp. 359
Requires Two Adjacent PCI Connectorsp. 363
High-Power AGP Pro Cardp. 364
Low-Power AGP Pro Cardp. 364
Card Power Indicationp. 365
Power Usagep. 365
Indexp. 369