Cover image for Computer organization and architecture : designing for performance
Title:
Computer organization and architecture : designing for performance
Author:
Stallings, William.
Personal Author:
Edition:
Fifth edition.
Publication Information:
Upper Saddle River, N.J. : Prentice Hall, [2000]

©2000
Physical Description:
xix, 748 pages : illustrations ; 24 cm
Language:
English
ISBN:
9780130812940
Format :
Book

Available:*

Library
Call Number
Material Type
Home Location
Status
Central Library QA76.9.C643 S73 2000 FIFTH EDITION Adult Non-Fiction Central Closed Stacks
Searching...

On Order

Summary

Summary

Addresses fundamental principles in computer organization and architecture and the critical role of performance in driving computer design, covering superscalar design, IA-64 design features, and parallel processor organization trends. Offers numerous ongoing examples, especially of Pentium, plus de


Author Notes

WILLIAM STALLINGS has made a unique contribution to understanding the broad sweep of technical developments in computer networking and computer architecture. He has authored 17 titles, plus revised editions, for a total of 37 books on various aspects of these subjects. He has three times received the award for best Computer Science Textbook of the Year from the Text and Academic Authors Association (Computer Organization and Architecture, Prentice Hall, 1996; Data and Computer Communications, Prentice Hall, 1997; Operating Systems, Prentice Hall, 1998).
In over 20 years in the field, Dr. Stallings has been a technical contributor, technical manager and an executive with several high-technology firms. Currently he is an independent consultant whose clients have included computer and networking manufacturers and customers, software development firms and leading-edge government research institutions. Dr. Stallings is a frequent lecturer and a regular contributor to technical journals and trade publications.
Dr. Stallings holds a Ph.D. from MIT in computer science and a B.S. from Notre Dame in electrical engineering.


Table of Contents

Web Sitep. vi
Prefacep. ix
Part I Overviewp. 1
Chapter 1 Introductionp. 3
1.1 Organization and Architecturep. 5
1.2 Structure and Functionp. 6
1.3 Outline of the Bookp. 12
1.4 Internet and Web Resourcesp. 15
Chapter 2 Computer Evolution and Performancep. 17
2.1 A Brief History of Computersp. 19
2.2 Designing for Performancep. 39
2.3 Pentium and PowerPC Evolutionp. 43
2.4 Recommended Reading and Web Sitesp. 46
2.5 Problemsp. 47
Part II The Computer Systemp. 49
Chapter 3 System Busesp. 51
3.1 Computer Componentsp. 53
3.2 Computer Functionp. 56
3.3 Interconnection Structuresp. 69
3.4 Bus Interconnectionp. 71
3.5 PCIp. 80
3.6 Recommended Reading and Web Sitesp. 89
3.7 Problemsp. 90
Appendix 3A Timing Diagramsp. 92
Chapter 4 Internal Memoryp. 95
4.1 Computer Memory System Overviewp. 97
4.2 Semiconductor Main Memoryp. 103
4.3 Cache Memoryp. 117
4.4 Pentium II and PowerPC Cache Organizationsp. 132
4.5 Advanced DRAM Organizationp. 137
4.6 Recommended Reading and Web Sitesp. 142
4.7 Problemsp. 143
Appendix 4A Performance Characteristics of Two-Level Memoriesp. 145
Chapter 5 External Memoryp. 153
5.1 Magnetic Diskp. 155
5.2 RAIDp. 163
5.3 Optical Memoryp. 172
5.4 Magnetic Tapep. 177
5.5 Recommended Reading and Web Sitesp. 178
5.6 Problemsp. 179
Chapter 6 Input/Outputp. 181
6.1 External Devicesp. 184
6.2 I/O Modulesp. 188
6.3 Programmed I/Op. 191
6.4 Interrupt-Driven I/Op. 195
6.5 Direct Memory Accessp. 203
6.6 I/O Channels and Processorsp. 207
6.7 The External Interface: SCSI and FireWirep. 209
6.8 Recommended Reading and Web Sitesp. 223
6.9 Problemsp. 224
Chapter 7 Operating System Supportp. 227
7.1 Operating System Overviewp. 229
7.2 Schedulingp. 241
7.3 Memory Managementp. 247
7.4 Pentium II and PowerPC Memory Managementp. 259
7.5 Recommended Reading and Web Sitesp. 268
7.6 Problemsp. 269
Part III The Central Processing Unitp. 271
Chapter 8 Computer Arithmeticp. 273
8.1 The Arithmetic and Logic Unit (ALU)p. 275
8.2 Integer Representationp. 276
8.3 Integer Arithmeticp. 282
8.4 Floating-Point Representationp. 298
8.5 Floating-Point Arithmeticp. 305
8.6 Recommended Reading and Web Sitesp. 314
8.7 Problemsp. 315
Appendix 8A Number Systemsp. 317
Chapter 9 Instruction Sets: Characteristics and Functionsp. 323
9.1 Machine Instruction Characteristicsp. 325
9.2 Types of Operandsp. 331
9.3 Pentium II and PowerPC Data Typesp. 333
9.4 Types of Operationsp. 336
9.5 Pentium II and PowerPC Operation Typesp. 349
9.6 Assembly Languagep. 358
9.7 Recommended Readingp. 360
9.8 Problemsp. 360
Appendix 9A Stacksp. 364
Appendix 9B Little-, Big-, and Bi-Endianp. 368
Chapter 10 Instruction Sets: Addressing Modes and Formatsp. 373
10.1 Addressingp. 375
10.2 Pentium and PowerPC Addressing Modesp. 382
10.3 Instruction Formatsp. 388
10.4 Pentium and PowerPC Instruction Formatsp. 397
10.5 Recommended Readingp. 402
10.6 Problemsp. 402
Chapter 11 CPU Structure and Functionp. 405
11.1 Processor Organizationp. 407
11.2 Register Organizationp. 409
11.3 The Instruction Cyclep. 414
11.4 Instruction Pipeliningp. 419
11.5 The Pentium Processorp. 434
11.6 The PowerPC Processorp. 443
11.7 Recommended Readingp. 450
11.8 Problemsp. 451
Chapter 12 Reduced Instruction Set Computersp. 455
12.1 Instruction Execution Characteristicsp. 458
12.2 The Use of a Large Register Filep. 462
12.3 Compiler-Based Register Optimizationp. 467
12.4 Reduced Instruction Set Architecturep. 469
12.5 RISC Pipeliningp. 476
12.6 MIPS R4000p. 480
12.7 SPARCp. 488
12.8 The RISC versus CISC Controversyp. 494
12.9 Recommended Readingp. 495
12.10 Problemsp. 496
Chapter 13 Instruction-Level Parallelism and Superscalar Processorsp. 499
13.1 Overviewp. 501
13.2 Design Issuesp. 506
13.3 Pentium IIp. 515
13.4 PowerPCp. 521
13.5 MIPS R10000p. 529
13.6 UltraSPARC-IIp. 531
13.7 IA-64/Mercedp. 534
13.8 Recommended Readingp. 545
13.9 Problemsp. 546
Part IV The Control Unitp. 551
Chapter 14 Control Unit Operationp. 553
14.1 Micro-operationsp. 555
14.2 Control of the Processorp. 561
14.3 Hardwired Implementationp. 573
14.4 Recommended Readingp. 575
14.5 Problemsp. 576
Chapter 15 Microprogrammed Controlp. 577
15.1 Basic Conceptsp. 579
15.2 Microinstruction Sequencingp. 588
15.3 Microinstruction Executionp. 593
15.4 TI 8800p. 605
15.5 Applications of Microprogrammingp. 615
15.6 Recommended Readingp. 616
15.7 Problemsp. 617
Part V Parallel Organizationp. 619
Chapter 16 Parallel Processingp. 621
16.1 Multiple Processor Organizationsp. 623
16.2 Symmetric Multiprocessorsp. 625
16.3 Cache Coherence and the MESI Protocolp. 635
16.4 Clustersp. 642
16.5 Nonuniform Memory Accessp. 646
16.6 Vector Computationp. 650
16.7 Recommended Readingp. 663
16.8 Problemsp. 664
Appendix A Digital Logicp. 669
A.1 Boolean Algebrap. 670
A.2 Gatesp. 672
A.3 Combinational Circuitsp. 675
A.4 Sequential Circuitsp. 696
A.5 Problemsp. 707
Appendix B Projects for Teaching Computer Organization and Architecturep. 709
B.1 Research Projectsp. 710
B.2 Simulation Projectsp. 710
B.3 Reading/Report Assignmentsp. 712
Glossaryp. 713
Referencesp. 725
Indexp. 739

Google Preview